U.S. Pat. No. 7,164,606 B1, which issued on Jan. 16, 2007, to Poplevine et al., discloses an all-PMOS 4-transistor non-volatile memory (NVM) cell that utilizes reverse Fowler-Nordheim tunneling for programming.
Referring to FIG. 1, as disclosed in U.S. Pat. No. 7,164,606, in accordance with the method of programming an NVM array that includes all-PMOS 4-transistor NVM cells having commonly-connected floating gates, for each cell in the array that is to be programmed, all of the electrodes of the cell are grounded. Then, an inhibiting voltage Vn is applied to the bulk-connected source region Vr of the cell's read transistor Pr, to the commonly-connected drain, bulk and source regions Ve of the cell's erase transistor Pe, and to the drain region Dr of the read transistor Pr. The source region Vp and the drain region Dp of the cell's programming transistor Pw are grounded. The bulk Vnw of the programming transistor Pw is optional; it can be grounded or it can remain at the inhibiting voltage Vn. For all cells in the array that are not selected for programming, the inhibiting voltage Vn is applied to electrodes Vr, Ve and Dr and is also applied to electrodes Vp, Dp and Vnw. The control voltage Vc of the cell's control transistor Pc is then swept from 0V to a maximum programming voltage Vcmax in a programming time Tprog. The control gate voltage Vc is then ramped down from the maximum programming voltage Vcmax to 0V. All electrodes of the cell and the inhibiting voltage Vn are then returned to ground.
As described in detail in the '606 patent, the all-PMOS 4-transistor NVM cell disclosed therein relies on reverse Fowler-Nordheim tunneling for programming. That is, when the potential difference between the floating gate electrode of the programming transistor of an all-PMOS NVM cell and the drain, source and bulk electrodes of the programming transistor exceeds a tunneling threshold voltage, electrons tunnel from the drain and source electrodes to the floating gate, making the floating gate negatively charged.
U.S. Pat. No. 7,164,606 is hereby incorporated by reference herein in its entirety to provide background information regarding the present invention.
The all-PMOS 4-transistor NVM cell programming technique disclosed in the '606 patent provides advantages of both low current consumption, allowing the ability to simultaneously program a large number of cells without the need for high current power sources, and a simple programming sequence. However, as discussed above, during the programming sequence, the drain and source regions of the read transistor Pr and of the programming transistor Pw of non-programmed NVM cells in the array are set to a fixed inhibiting voltage Vn, while the Ve electrode of the erase transistor Pe is set to the inhibiting voltage Vn and the Vc electrode of the control transistor Pc is ramped up from 0V to Vcmax. As a result, negative charge is trapped on the floating gate of the non-programmed cells, even though the amount of trapped charge is less than the negative charge that is trapped on the floating gate of the programmed cells. This sets the voltage level of the floating gate of a non-programmed cell to about Vn above the voltage level of the floating gate of a programmed cell. This means that the maximum possible voltage difference between the floating gate of a programmed cell and the floating gate of a non-programmed cell is Vn. Non-programmed cells with this condition are referred to as “disturbed cells.”
Thus, there is a need for an NVM cell design that increases the voltage difference between the floating gate of a programmed NVM cell and a non-programmed NVM cell, but retains the advantages of the all-PMOS 4 transistor NVM cell.